Mixed signal integrated circuits (ICs) provide both analog and digital circuitry on a common substrate. For example, a mixed signal IC may include one or more sensitive radio frequency (RF) analog circuits, such as a mixer, voltage-controlled oscillator (VCO) and low-noise amplifier (LNA), as well as one or more digital logic circuits, such as a digital signal processor (DSP) or frequency synthesizer. These RF circuits generally operate at frequencies of 1 Gigahertz (GHz) and above. One of the disadvantages inherent in conventional mixed signal ICs is the problem of isolating sensitive analog circuitry from the digital circuitry, which typically generates more noise, particularly in a radio frequency (RF) band of interest due at least in part to the sharp edges of the digital signals present in all continuously running digital logic circuitry. As the frequency of these digital signals increases, so does the noise generated by the digital circuitry.
For applications in an RF frequency range, digital noise generated by the digital logic circuitry is more effectively coupled to the sensitive analog circuitry through the common substrate and can adversely affect the operation of the analog circuitry. At RF frequencies, a dominant mechanism for coupling digital noise to the substrate becomes the drain-to-substrate capacitance associated with digital devices comprising the digital logic circuitry which becomes lower in impedance. Contributing to a reduced attenuation of the digital noise is the fact that the inductance of a substrate-to-ground connection is a higher impedance in an RF frequency range, thereby making it harder to shunt the digital noise to ground. A desired attenuation of the digital noise at RF frequencies is typically greater than 10,000 to 1 (i.e., >80 decibels (dB)).
Various techniques have been proposed and utilized in an attempt to isolate noisy digital circuitry from sensitive analog circuitry within the same IC, thereby reducing some or substantially all of the various noise problems caused by the digital circuitry. Such techniques include isolation by physical separation of the analog and digital sections of the IC; isolation by providing separate power supply rails; isolation by grounded guard rings/substrate trenches around the analog and/or digital section; employing differential circuitry in the sensitive analog section; use of low noise injecting digital circuitry, such as current steering logic; making the digital circuitry sections synchronous with the analog function; and moving the clock edges away from critical analog sampling instances. Such conventional approaches to noise reduction and/or isolation, however, are generally not always sufficient or fully effective, and may not be practical, feasible, or otherwise cost-effective to implement in a given application.
Conventionally, a low impedance substrate having a low impedance connection to ground has been utilized to achieve the above-noted 80 dB attenuation objective. However, the low impedance substrate, while generally used to reduce latch-up in digital complimentary metal-oxide-semiconductor (CMOS) circuitry, undesirably reduces the quality factor or Q of on-chip metal inductors. Another conventional technique, called triple-well, places an N-type buried layer under the digital CMOS circuitry. This buried layer is connected to ground at the edge of the digital logic area to shunt away some of the digital noise which would otherwise be coupled to the substrate.
Accordingly, there exists a need for techniques, for use in mixed signal ICs and other devices, that provide improved isolation, particularly in an RF frequency range of operation, between digital and analog circuitry residing on a common substrate.